LSI (Large Scale Integration) technology using silicon is an indispensable technology in modern society. For example, LSIs are mounted on personal computers and cellular phones. LSIs include something called a processor that processes information, such as a CPU (Central Processing Unit). To process more information, information processing has to proceed faster. Enhancement of device performance has been made so far mainly through device microfabrication. That is, the performance of transistors is increased through microfabrication of each transistor that processes information, thereby making it possible to operate at higher speeds. Performance enhancement through device microfabrication in this manner is called scaling, which has become a leading principle supporting the semiconductor industry.
However, with minimum processing dimension at a manufacturing level becoming less than 100 nm, a significant difficulty has occurs to further device microfabrication. For example, each transistor supporting a CPU is mainly a Metal Oxide Semiconductor Field Effect Transistor, and the film thickness of a gate insulating film of the MISFET is less than 2.0 nm. This is as thin as approximately ten atom layers. If the film is made to be thinner, a tunnel current flows directly through the gate insulating film, and a power consumption increases.
To solve this problem, research and development of a high-dielectric-constant gate insulating film with dielectric constant higher than that of conventional SiO2 (since a relative dielectric constant is often represented by k, this gate insulating film is referred to as a high-k film) has been actively performed around the world. It has been demonstrated that the tunnel current can be directly suppressed indeed by applying a high-k film to the gate insulating film of a transistor. However, it has been revealed that the mobility of a channel portion of the transistor (a region where a current flows in an ON state) is decreased with the use of a high-k film. The mobility represents a moving speed of a carrier in unit electric field, and its unit is cm2/Vs. As is evident from the definition, a decrease in mobility causes deterioration of operation speed of the transistor. This is a critical defect in achieving performance enhancement of the transistor.
As described above, an object of scaling the transistor is to process more information at higher speed. However, if the mobility is decreased at the risk of introducing a new material, that is, a high-k film, and a processing speed is decreased, this is a case of the tail wagging the dog. Therefore, although there are needs in industries desiring to introducing a high-k film in view of power consumption, application of a high-k film to a gate insulating film has not yet been in actual use. Therefore, in such a situation that material development of a high-k film has not yet been completed, the use of a conventional SiO2 film or an oxynitrided film (SiON) obtained by adding nitrogen to SiO2 has to be used continuously. That is, thinning the gate insulating film has to be frozen as a matter of practice, or proceeds at a significantly slow pace equal to or lower than approximately 1 angstrom for every several years. Since thinning the gate insulating film has played an extremely important role in pushing forward the scaling, the scaling of silicon semiconductor technology is in a crisis situation.
Therefore, new device technology developments with no depending on thinning of the gate insulating film have proceed. Since these technologies are not an extension of simple microfabrication, these are called technology boosters. Of such technology boosters, the one that should be noted is an approach of directly increasing the mobility of the silicon transistor. As described above, as the mobility is increased, the carrier moves faster and, as a matter of course, the processing speed of the field-effect transistor becomes faster by that amount.
One scheme for increasing the mobility is a strained-silicon transistor technology. The strained-silicon technology is a technology for increasing the mobility of the carrier by applying a strain to silicon.
Several schemes to apply a strain have been known. For example, in one scheme, by epitaxially growing silicon on silicon germanium epitaxially grown on a silicon substrate, tensile strain is applied to silicon, as shown in “J. Welser, Technical Digest of International Electron Device Meeting, 1994, pp. 373-376” (Non-Patent Document 1) and “N. Sugii, Technical Digest of International Electron Device Meeting, 2002, pp. 737-740” (Non-Patent Document 2). In another known scheme, by depositing a silicon nitride film as a liner film on a field-effect transistor, a compressive or tensile strain is applied to a channel portion, as shown in “F. Ootsuka, Technical Digest of International Electron Device Meeting, 2000, pp. 575-578” (Non-Patent Document 3). In still another known scheme, a compressive strain is applied to a channel portion by a strain caused by Shallow Trench Isolation used in device isolation, so that the hole mobility is increased, as shown in Non-Patent Document 3. In still another known scheme, as shown in “P. Bai, Technical Digest of International Electron Device Meeting, 2004, pp. 657-660” (Non-Patent Document 4), by epitaxially growing a silicon germanium in vicinity of a source-drain diffusion layer, a compressive strain is selectively applied to a channel portion of a p-type filed-effect transistor in parallel to a channel direction.
As described above, schemes of applying a strain through various manufacturing processes have been known. In any of these schemes, the mobility is increased to increase a driving current, thereby making it possible to exchange electrical charge within a shorter time and, as a result, an increase in processing speed is achieved.
Also, one technological scheme for increasing the driving current of the p-type field-effect transistor without special consideration of the manufacturing method, in which a <100> direction on a (100) substrate is taken as a channel direction, has been known, as shown in “H. Sayama, Technical Digest of International Electron Device Meeting, 1999, pp. 657-660” (Non-Patent Document 5).
Also, as technology booster other than that for increasing the driving current, a scheme using a transistor called FinFET having a three-dimensional structure, has been known, as shown in “D. Hisamoto, Technical Digest of International Electron Device Meeting, 1998, pp. 1032-1043” (Non-Patent Document 6). In the FinFET, by taking a finely-divided Silicon On Insulator called Fin as a channel portion, and interposing the Fin three-dimensionally between a gate insulating film and a gate electrode, a channel is formed on both sides of the Fin, and as a result, a short-channel effect is suppressed. With the use of the FinFET, further scaling is expected.